1. Field of the Invention
The present invention relates to a semiconductor memory with a trench capacitor, such as DRAM array, and a method of fabricating the same.
2. Description of the Related Art
Performance of dynamic random access memory (DRAM) arrays has been improved with reduction in their size. However, short-channel effects of transistors have become intense with reduction in the size of the DRAM arrays, whereupon the performance of DRAM arrays has been reduced. In view of this problem, an acceptor impurity such as boron (B) has been implanted into a channel region of a cell transistor to adjust a cutoff characteristic of the cell transistor. The foregoing problem has been overcome by adjusting an amount of the impurity.
However, when the density of impurity implanted to the channel region of the cell transistor is increased in order that the short-channel effects may be suppressed, the impurity density in a source/drain region of the cell transistor is also increased, whereupon a data-hold time of the memory cell is rendered shorter as the result of the increase in the impurity density in the source/drain region. Accordingly, JP-A-2000-31412 discloses a method of suppressing reduction in the data-hold time of the memory cell while the threshold voltage is suppressed from drop due to the short-channel effects.
In JP-A-2000-31412, impurity is implanted into the channel region in a direction oblique to the cell transistor so that the impurity density is increased in the channel region of the cell transistor and further so that no impurity is implanted into the source/drain region which becomes the shadow of the cell transistor, whereby the impurity density is suppressed from being increased in the source/drain region.
In DRAM with the trench capacitor structure, however, leak current (junction leak current) is increased in a junction of the capacitor side diffusion layer of the cell capacitor when the density of impurity diffused to the channel region of the cell transistor. As a result, a discharging speed of the trench capacitor is increased. Further, when the trench capacitor is brought into electrical contact with the transistor at a location lower than the upper side of the silicon semiconductor substrate, occurrence of punch-through at a deeper location is a matter of concern. The above-mentioned document discloses nothing about these respects.